1. Field of the Invention
The present invention relates to an electrically writable nonvolatile memory.
2. Description of the Background Art
Conventionally, in electrically writable nonvolatile memories, for example, as disclosed by U.S. Patent Application Publication No. 2005/0024966 A1 to Oyama and U.S. Pat. No. 5,132,933 to Schreck et al., a plurality of memory cells are connected to wordlines (WLs) and bitlines (BLs) to form a memory cell array, in which a bitline (BL) connected to a memory cell to be read is connected through a cell selector to a cell-reading amplifier, and a current of the selected memory cell is compared with a current of a reference memory cell to read-out data.
In this case, the cell-reading amplifier employs a cell source voltage (CSV) level as a reference voltage, and a voltage of a bitline in a stable condition is approximately equal to the cell source voltage.
In the conventional systems, when switching memory cells which are to be read, memory cells that are connected to a reference bitline are always in the same direction. Therefore, there is no large change in the amount of current flowing through the reference bitline. However, memory cells that are to be read include both a zero-read cell for reading a bit “zero” and a one-read cell for reading a bit “one”. Because of this, when a zero-read cell is read after a one-read cell is read, current flows until the bitline is charged to some extent, and therefore, it takes time to determine whether a bit “zero” has been read. This requires, for example, 70 nanoseconds, resulting in an access delay.